1. Field of the Invention
The present invention relates to radiation hardened (xe2x80x9cradhardxe2x80x9d) power integrated circuits which have improved resistance to damage by large (megarad) doses of ionizing radiation, or by single or plural event high energy charged particles.
2. Brief Description of the Related Art
Power integrated circuits (PICs) are well known in the prior art. PICs typically include circuitry for controlling MOS-gated power transistors. In some PICs, the MOS-gated power transistors are integrated into the same silicon that carries the control circuitry. A typical PIC of this type is the IR2112 PIC made by the International Rectifier Corporation.
The PICs like most electronic devices, do not function well in a high radiation environment, such as in outer space. The effects of ionizing radiation can accumulate over time, resulting in device degradation. Also, heavy ion strikes can lead to catastrophic failure. When power devices are employed in such environments, the devices are typically more susceptible to these problems because of their large depletion volumes and large device areas. Power MOS-gated devices specifically designed for use in radiation-rich environments, commonly termed radhard devices, are well known. Such devices are described in U.S. Pat. Nos. 5,338,693; 5,831,318;and 6,165,821 which are assigned to the assignee of the present application. The design rules for such radhard devices are quite different from those of conventional MOS-gated devices, such as power MOSFETs, IGBTs MOSgated thyristors and the like. These different design rules arise to ensure the continued operation of the MOS-gated device in an ionizing radiation environment. The design rules generally call for the use of the thinnest possible gate oxide (for example, about 700 to 900 xc3x85 for a 400 volt reverse breakdown device) to minimize threshold voltage shift in the presence of a high radiation background. A xe2x80x9clate gatexe2x80x9d process sequence is also employed which reduces the exposure of the gate oxide to high temperature process steps. It would be desirable to provide a radhard PIC that utilizes the above-noted design features and can function in a high radiation environment.
The present invention overcomes the deficiencies in the prior art, such as those described above, by providing a xe2x80x9cradhardxe2x80x9d PIC (that is, a PIC that can operate in a high radiation environment). A discussion of radiation resistance in electronic devices as it relates to total dose and single event considerations is provided in U.S. Pat. No. 6,165,821 issued Dec. 26, 2000, the entire disclosure of which is incorporated herein by reference.
The PIC of the present invention includes a latch-up immune 20V CMOS and a 600V LDMOS. The novel device provides high voltage operation that can control loads of, for example, about 400 volts to at least 600 volts. Using the novel production process in which gate oxides are formed late in the process, the gate oxides are not exposed to high temperature processing steps, making the devices less susceptible to damage in high ionizing radiation environments. A high voltage, junction isolation (HVJI) process is used. The HVJI process is disclosed in U.S. Pat. No. 5,023,678 issued Jun. 11, 1991, the entire disclosure of which is incorporated herein by reference.
A preferred process for manufacturing a radiation hardened power integrated circuit according to the present invention includes steps for enhancing TID and SEE capabilities.
Enhanced TID hardness is provided by forming gate oxides late in a high voltage, junction isolation process so as to avoid exposing the gate oxides to high temperature processing steps. In addition, two implant layers are included in the CMOS to raise the parasitic MOSFET thresholds with respect to native thresholds. Preferably, a radhard field oxide is provided as well. The layout of the device accounts for these processes and suppresses CMOS drain to source and intra-well transistor-to-transistor leakage, in particular with respect to polygate to field oxide overlap and individual ringing of CMOS devices with channel adjust layers.
SEE ruggedness is provided by a reduced epi thickness and increased epitaxial layer (epi) concentration near the substrate junction. Accordingly, the device has reduced charge collection volume and reduced parasitic bipolar gain, which in turn provides a reduced chance of a single event latch-up condition after a heavy ion strike. The increase epi concentration near the substrate junction also has the added benefit of truncating charge funneling effects in the silicon.
The PIC thus produced demonstrates total ionizing dose (TID) capabilities of at least 100 krads, and single event effects (SEE) capabilities in terms of linear energy transfer coefficient (LET) of at least 37 MeV/(mg/cm2) at full rated voltage.